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1. general description the pca9544a is a 1-of-4 bidirectional translating multiplexer, controlled via the i 2 c-bus. the scl/sda upstream pair fans out to four scx/sdx downstream pairs, or channels. only one scx/sdx channel is selected at a time, determined by the contents of the programmable control register. four interrupt inputs, int0 to int3, one for each of the scx/sdx downstream pairs, are provided. one interrupt output, int, which acts as an and of the four interrupt inputs, is provided. a power-on reset function puts the registers in their default state and initializes the i 2 c-bus state machine with no channels selected. the pass gates of the multiplexer are constructed such that the v dd pin can be used to limit the maximum high voltage which will be passed by the pca9544a. this allows the use of different bus voltages on each scx/sdx pair, so that 1.8 v, 2.5 v or 3.3 v parts can communicate with 5 v parts without any additional protection. external pull-up resistors pull the bus up to the desired voltage level for each channel. all i/o pins are 5 v tolerant. 2. features n 1-of-4 bidirectional translating multiplexer n i 2 c-bus interface logic; compatible with smbus n 4 active low interrupt inputs n active low interrupt output n 3 address pins allowing up to 8 devices on the i 2 c-bus n channel selection via i 2 c-bus n power-up with all multiplexer channels deselected n low r on switches n allows voltage level translation between 1.8 v, 2.5 v, 3.3 v and 5 v buses n no glitch on power-up n supports hot insertion n low standby current n operating power supply voltage range of 2.3 v to 5.5 v n 5 v tolerant inputs n 0 hz to 400 khz clock frequency n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n three packages offered: so20, tssop20 and hvqfn20 pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic rev. 03 24 november 2008 product data sheet
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 2 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version PCA9544AD so20 plastic small outline package; 20 leads; body width 7.5 mm sot163-1 pca9544apw tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 pca9544abs hvqfn20 plastic thermal enhanced very thin quad ?at package; no leads; 20 terminals; body 5 5 0.85 mm sot662-1 table 2. ordering options type number topside mark temperature range PCA9544AD PCA9544AD - 40 c to +85 c pca9544apw pa9544a - 40 c to +85 c pca9544abs 9544a - 40 c to +85 c
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 3 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 4. block diagram fig 1. block diagram switch control logic pca9544a power-on reset 002aae296 sd2 sd3 v ss v dd i 2 c-bus control input filter scl sda a0 a1 a2 sd1 sd0 sc2 sc3 sc1 sc0 interrupt logic int[3:0] int
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 4 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 5. pinning information 5.1 pinning fig 2. pin con?guration for so20 fig 3. pin con?guration for tssop20 fig 4. pin con?guration for hvqfn20 PCA9544AD a0 v dd a1 sda a2 scl int0 int sd0 sc3 sc0 sd3 int1 int3 sd1 sc2 sc1 sd2 v ss int2 002aae293 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 a0 v dd a1 sda a2 scl int0 int sd0 sc3 sc0 sd3 int1 int3 sd1 sc2 sc1 sd2 v ss int2 pca9544apw 002aae294 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 002aae295 pca9544abs transparent top view sc2 sc0 int1 int3 sd0 sd3 int0 sc3 a2 int sd1 sc1 v ss int2 sd2 a1 a0 v dd sda scl 5 11 4 12 3 13 2 14 1 15 6 7 8 9 10 20 19 18 17 16 terminal 1 index area
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 5 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 5.2 pin description [1] hvqfn20 package supply ground is connected to both v ss pin and exposed center pad. v ss pin must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. table 3. pin description symbol pin description so20, tssop20 hvqfn20 a0 1 19 address input 0 a1 2 20 address input 1 a2 3 1 address input 2 int0 4 2 active low interrupt input 0 sd0 5 3 serial data 0 sc0 6 4 serial clock 0 int1 7 5 active low interrupt input 1 sd1 8 6 serial data 1 sc1 9 7 serial clock 1 v ss 10 8 [1] supply ground int2 11 9 active low interrupt input 2 sd2 12 10 serial data 2 sc2 13 11 serial clock 2 int3 14 12 active low interrupt input 3 sd3 15 13 serial data 3 sc3 16 14 serial clock 3 int 17 15 active low interrupt output scl 18 16 serial clock line sda 19 17 serial data line v dd 20 18 supply voltage
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 6 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 6. functional description refer to figure 1 bloc k diag r am . 6.1 device addressing following a start condition the bus master must output the address of the slave it is accessing. the address of the pca9544a is shown in figure 5 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low. the last bit of the slave address de?nes the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. 6.2 control register following the successful acknowledgement of the slave address, the bus master will send a byte to the pca9544a which will be stored in the control register. if multiple bytes are received by the pca9544a, it will save the last byte received. this register can be written and read via the i 2 c-bus. 6.2.1 control register de?nition a scx/sdx downstream pair, or channel, is selected by the contents of the control register. this register is written after the pca9544a has been addressed. the 3 lsbs of the control byte are used to determine which channel is to be selected. when a channel is selected, it will become active after a stop condition has been placed on the i 2 c-bus. this ensures that all scx/sdx lines will be in a high state when the channel is made active, so that no false conditions are generated at the time of connection. fig 5. slave address 002aab189 1 1 1 0 a2 a1 a0 r/w fixed hardware selectable fig 6. control register 002aae297 int3 int2 int1 int0 x b2 b1 b0 interrupt bits (read only) channel selection bits (read/write) 76543210 bit enable bit
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 7 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 6.3 interrupt handling the pca9544a provides 4 interrupt inputs, one for each channel and one open-drain interrupt output. when an interrupt is generated by any device, it will be detected by the pca9544a and the interrupt output will be driven low. the channel need not be active for detection of the interrupt. a bit is also set in the control byte. bits 7:4 of the control byte correspond to channel 3 to channel 0 of the pca9544a, respectively. therefore, if an interrupt is generated by any device connected to channel 2, the state of the interrupt inputs is loaded into the control register when a read is accomplished. likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. the master can then address the pca9544a and read the contents of the control byte to determine which channel contains the device generating the interrupt. the master can then recon?gure the pca9544a to select this channel, and locate the device generating the interrupt and clear it. the interrupt clears when the device originating the interrupt clears. it should be noted that more than one device can be providing an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. the interrupt inputs may be used as general purpose inputs if the interrupt function is not required. if unused, interrupt input(s) must be connected to v dd through a pull-up resistor. remark: several interrupts can be active at the same time. for example: int3 = 0, int2 = 1, int1 = 1, int0 = 0, means that there is no interrupt on channel 0 and channel 3, and there is an interrupt on channel 1 and on channel 2. table 4. control register: writechannel selection; readchannel status int3 int2 int1 int0 d3 b2 b1 b0 command xxxxx0 xx no channel selected xxxxx 1 0 0 channel 0 enabled xxxxx 1 0 1 channel 1 enabled xxxxx 1 1 0 channel 2 enabled xxx0 x 1 1 1 channel 3 enabled 00000000no channel selected; power-up default state table 5. control register read interrupt int3 int2 int1 int0 d3 b2 b1 b0 command xxx 0 xxxx no interrupt on channel 0 1 interrupt on channel 0 xx 0 xxxxx no interrupt on channel 1 1 interrupt on channel 1 x 0 xxxxxx no interrupt on channel 2 1 interrupt on channel 2 0 xxxxxxx no interrupt on channel 3 1 interrupt on channel 3
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 8 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 6.4 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca9544a in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pca9544a registers and i 2 c-bus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. thereafter, v dd must be lowered below 0.2 v to reset the device. 6.5 voltage translation the pass gate transistors of the pca9544a are constructed such that the v dd voltage can be used to limit the maximum voltage that will be passed from one i 2 c-bus to another. figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data speci?ed in section 11 dynamic char acter istics of this data sheet). in order for the pca9544a to act as a voltage translator, the v o(sw) voltage should be equal to, or lower than the lowest bus voltage. for example, if the main bus was running at 5 v, and the downstream buses were 3.3 v and 2.7 v, then v o(sw) should be equal to or below 2.7 v to effectively clamp the downstream bus voltages. looking at figure 7 , we see that v o(sw)(max) will be at 2.7 v when the pca9544a supply voltage is 3.5 v or lower so the pca9544a supply voltage could be set to 3.3 v. pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see figure 14 ). more information can be found in application note an262, pca954x family of i 2 c/smbus multiplexers and switches . (1) maximum (2) typical (3) minimum fig 7. pass gate voltage versus supply voltage v dd (v) 2.0 5.5 4.5 3.0 4.0 002aaa964 3.0 2.0 4.0 5.0 v o(sw) (v) 1.0 3.5 5.0 2.5 (1) (2) (3)
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 9 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 7. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 8 ). 7.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 9 ). 7.3 system con?guration a device generating a message is a transmitter, a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 10 ). fig 8. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 9. de?nition of start and stop conditions mba608 sda scl p stop condition sda scl s start condition
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 10 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 7.4 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse so that the sda line is stable low during the high period of the acknowledge related clock pulse; setup and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 10. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 11. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 11 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 7.5 bus transactions fig 12. write control register fig 13. read control register 002aae299 xxxxxb2b1b0 1 1 0 a2 a1 a0 0 a s 1 a p slave address start condition r/w acknowledge from slave acknowledge from slave control register sda stop condition 002aae300 int 3 int 2 int 1 int 0 x b2b1b0 1 1 0 a2 a1 a0 1 a s 1 na p slave address start condition r/w acknowledge from slave no acknowledge from master control register sda stop condition last byte
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 12 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 8. application design-in information (1) if the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. if the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a pull-up resistor is not required. the interrupt inputs should not be left ?oating. fig 14. typical application pca9544a sd0 sc0 a1 a0 v ss sda scl int v dd = 3.3 v v dd = 2.7 v to 5.5 v i 2 c-bus/smbus master 002aae298 sda scl channel 0 v = 2.7 v to 5.5 v a2 int0 (1) sd1 sc1 channel 1 v = 2.7 v to 5.5 v int1 (1) sd2 sc2 channel 2 v = 2.7 v to 5.5 v int2 (1) sd3 sc3 channel 3 v = 2.7 v to 5.5 v int3 (1)
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 13 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 9. limiting values [1] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not exceed 125 c. table 6. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to ground (v ss = 0 v). [1] symbol parameter conditions min max unit v dd supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i i input current - 20 ma i o output current - 25 ma i dd supply current - 100 ma i ss ground supply current - 100 ma p tot total power dissipation - 400 mw t stg storage temperature - 60 +150 c t amb ambient temperature operating - 40 +85 c
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 14 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 10. static characteristics [1] for operation between published voltage ranges, refer to worst case parameter in both ranges. [2] v dd must be lowered to 0.2 v in order to reset part. table 7. static characteristics v dd = 2.3 v to 3.6 v ; v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. see t ab le 8 for v dd = 4.5 v to 5.5 v. [1] symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 3.6 v i dd supply current operating mode; v dd = 3.6 v; no load; v i =v dd or v ss ; f scl = 100 khz -1030 m a i stb standby current standby mode; v dd = 3.6 v; no load; v i =v dd or v ss ; f scl = 0 khz - 0.1 1 m a v por power-on reset voltage no load; v i =v dd or v ss [2] - 1.5 2.1 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 7 - ma v ol = 0.6 v 6 10 - ma i l leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss -1013 pf select inputs a0 to a2, int0 to int3 v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -v dd + 0.5 v i li input leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss - 1.6 3 pf pass gate r on on-state resistance v dd = 3.0 v to 3.6 v; v o = 0.4 v; i o =15ma 51130 w v dd = 2.3 v to 2.7 v; v o = 0.4 v; i o =10ma 71655 w v o(sw) switch output voltage v i(sw) =v dd = 3.3 v; i o(sw) = - 100 m a - 1.9 - v v i(sw) =v dd = 3.0 v to 3.6 v; i o(sw) = - 100 m a 1.6 - 2.8 v v i(sw) =v dd = 2.5 v; i o(sw) = - 100 m a - 1.5 - v v i(sw) =v dd = 2.3 v to 2.7 v; i o(sw) = - 100 m a 1.1 - 2.0 v i l leakage current v i =v dd or v ss - 1- +1 m a c io input/output capacitance v i =v ss -35 pf int output i ol low-level output current v ol = 0.4 v 3 7 - ma i oh high-level output current - - +10 m a
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 15 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic [1] for operation between published voltage ranges, refer to worst case parameter in both ranges. [2] v dd must be lowered to 0.2 v in order to reset part. table 8. static characteristics v dd = 4.5 v to 5.5 v ; v ss =0v; t amb = - 40 c to +85 c; unless otherwise speci?ed. see t ab le 7 for v dd = 2.3 v to 3.6 v. [1] symbol parameter conditions min typ max unit supply v dd supply voltage 4.5 - 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; v i =v dd or v ss ; f scl = 100 khz - 25 100 m a i stb standby current standby mode; v dd = 5.5 v; no load; v i =v dd or v ss ; f scl = 0 khz - 0.3 1 m a v por power-on reset voltage no load; v i =v dd or v ss [2] - 1.7 2.1 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -6 v i ol low-level output current v ol = 0.4 v 3 - - ma v ol = 0.6 v 6 - - ma i l leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss -1213 pf select inputs a0 to a2, int0 to int3 v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -v dd + 0.5 v i li input leakage current pin at v dd or v ss - 1- +1 m a c i input capacitance v i =v ss -25 pf pass gate r on on-state resistance v dd = 4.5 v to 5.5 v; v o = 0.4 v; i o =15ma 4924 w v o(sw) switch output voltage v i(sw) =v dd = 5.0 v; i o(sw) = - 100 m a - 3.6 - v v i(sw) =v dd = 4.5 v to 5.5 v; i o(sw) = - 100 m a 2.6 - 4.5 v i l leakage current v i =v dd or v ss - 1- +1 m a c io input/output capacitance v i =v ss -35 pf int output i ol low-level output current v ol = 0.4 v 3 - - ma i oh high-level output current - - +10 m a
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 16 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 11. dynamic characteristics [1] pass gate propagation delay is calculated from the 20 w typical r on and the 15 pf load capacitance. [2] after this period, the ?rst clock pulse is generated. [3] a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ih(min) of the scl signal) in order to bridge the unde?ned region of the falling edge of scl. [4] c b = total capacitance of one bus line in pf. [5] measurements taken with 1 k w pull-up resistor and 50 pf load. table 9. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t pd propagation delay from sda to sdn, or scl to scn - 0.3 [1] - 0.3 [1] ns f scl scl clock frequency 0 100 0 400 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - m s t hd;sta hold time (repeated) start condition [2] 4.0 - 0.6 - m s t low low period of the scl clock 4.7 - 1.3 - m s t high high period of the scl clock 4.0 - 0.6 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - m s t hd;dat data hold time 0 [3] 3.45 0 [3] 0.9 m s t su;dat data set-up time 250 - 100 - ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [4] 300 ns t f fall time of both sda and scl signals - 300 20 + 0.1c b [4] 300 m s c b capacitive load for each bus line - 400 - 400 m s t sp pulse width of spikes that must be suppressed by the input ?lter - 50 - 50 ns t vd;dat data valid time high-to-low [5] -1 - 1 m s low-to-high [5] - 0.6 - 0.6 m s t vd;ack data valid acknowledge time - 1 - 1 m s int t v(intnn-intn) valid time from intn to int signal [5] -4 - 4 m s t d(intnn-intn) delay time from intn to int inactive [5] -2 - 2 m s t w(rej)l low-level rejection time intn inputs [5] 1- 1 - m s t w(rej)h high-level rejection time intn inputs [5] 0.5 - 0.5 - m s
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 17 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic fig 15. de?nition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 18 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 12. package outline fig 16. package outline sot163-1 (so20) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 19 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic fig 17. package outline sot360-1 (tssop20) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 20 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic fig 18. package outline sot662-1 (hvqfn20) 0.65 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 2.6 e 2 2.6 0.38 0.23 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot662-1 mo-220 - - - - - - 0.75 0.50 l 0.1 v 0.05 w 0 2.5 5 mm scale sot662-1 hvqfn20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 610 20 16 15 11 5 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-22 a c c b v m w m e (1) d (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included.
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 21 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 22 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 13.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 19 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 10 and 11 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 19 . table 10. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 11. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 23 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 14. abbreviations msl: moisture sensitivity level fig 19. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 12. abbreviations acronym description cdm charged-device model esd electrostatic discharge hbm human body model i/o input/output i 2 c-bus inter-integrated circuit bus lsb least signi?cant bit mm machine model pcb printed-circuit board por power-on reset smbus system management bus
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 24 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 15. revision history table 13. revision history document id release date data sheet status change notice supersedes pca9544a_3 20081124 product data sheet - pca9544a_2 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? section 2 f eatures : C 8 th bullet item: changed from rds on to r on C 16 th bullet item: changed from and 1000 v per jesd22-c101 to and 1000 v cdm per jesd22-c101 ? section 5.1 pinning : added separate pinning diagrams for so20 and tssop20 ? t ab le 3 pin descr iption : added t ab le note [1] and its reference at hvqfn20 pin 8 (v ss ) ? section 6.5 v oltage tr anslation : changed symbol from v pass to v o(sw) ? figure 14 t ypical application : corrected signal names: C for channel 2, changed sd1 and sc1 to sd2 and sc2 C for channel 3, changed sd1 and sc1 to sd3 and sc3 ? t ab le 6 limiting v alues : C changed parameter for i ss from supply current to ground supply current C changed parameter for t amb from operating ambient temperature to ambient temperature (moved operating to conditions column) C deleted (old) table note 1 (this statement is now located in section 16.3 disclaimers , paragraph limiting values) C t ab le note [1] , 2 nd sentence: changed from should not exceed 150 c to should not exceed 125 c ? t ab le 7 static char acter istics (v dd = 2.3 v to 3.6 v): C table title changed from dc characteristics to static characteristics C descriptive line below table title: changed from see t ab le 8 for v dd = 3.6 v to 5.5 v. to see t ab le 8 for v dd = 4.5 v to 5.5 v. C sub-section pass gate: changed symbol/parameter from r on , switch resistance to r on , on-state resistance C sub-section pass gate: changed symbol from v pass to v o(sw) C sub-section pass gate, conditions column: changed symbol from v swin to v i(sw) ; changed symbol from i swout to i o(sw) ? t ab le 8 static char acter istics (v dd = 4.5 v to 5.5 v): C table title changed from dc characteristics to static characteristics C sub-section pass gate: changed symbol/parameter from r on , switch resistance to r on , on-state resistance C sub-section pass gate: changed symbol from v pass to v o(sw) C sub-section pass gate, conditions column: changed symbol from v swin to v i(sw) ; changed symbol from i swout to i o(sw)
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 25 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic modi?cations: (continued) ? t ab le 9 dynamic char acter istics : C symbol t hd;sta : phrase after this period, the ?rst clock pulse is generated. has been moved to t ab le note [2] C symbols t vd:datl and t vd:dath merged to form t vd;dat (and added conditions high-to-low and low-to-high) C sub-section int re-written in its entirety ? added soldering information ? added section 14 ab bre viations pca9544a_2 (9397 750 13931) 20040929 product data sheet - pca9544a_1 pca9544a_1 (9397 750 13301) 20040728 objective data sheet - - table 13. revision history continued document id release date data sheet status change notice supersedes
pca9544a_3 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 03 24 november 2008 26 of 27 nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pca9544a 4-channel i 2 c-bus multiplexer with interrupt logic ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 24 november 2008 document identifier: pca9544a_3 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 device addressing . . . . . . . . . . . . . . . . . . . . . . 6 6.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2.1 control register de?nition . . . . . . . . . . . . . . . . . 6 6.3 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 7 6.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.5 voltage translation . . . . . . . . . . . . . . . . . . . . . . 8 7 characteristics of the i 2 c-bus. . . . . . . . . . . . . . 9 7.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.2 start and stop conditions . . . . . . . . . . . . . . 9 7.3 system con?guration . . . . . . . . . . . . . . . . . . . . 9 7.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.5 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11 8 application design-in information . . . . . . . . . 12 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 10 static characteristics. . . . . . . . . . . . . . . . . . . . 14 11 dynamic characteristics . . . . . . . . . . . . . . . . . 16 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 13 soldering of smd packages . . . . . . . . . . . . . . 21 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 21 13.2 wave and re?ow soldering . . . . . . . . . . . . . . . 21 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 13.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 26 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17 contact information. . . . . . . . . . . . . . . . . . . . . 26 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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